The 1st ACM/IEEE International Symposium on Networks-on-Chip

Presentation slides linked to the Program page

Click here to view pictures from the symposium

General Information

Network-on-Chip (NoC) is an emerging paradigm using packet-switched networks for communications within large VLSI systems on-chip. NoCs are poised to provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures such as busses and dedicated signal wires. The NOC symposium brings together academic and industrial researchers and developers addressing issues of NoC-based systems at all levels, from the physical on-chip link level through the network level, and ranging up to system architecture and application software.

GENERAL CO-CHAIRS

PROGRAM COMMITTEE CO-CHAIRS
Eby Friedman, Rochester, USA
Wayne Wolf, Princeton, USA 		Avi Kolodny, Technion , Israel
Li-Shiuan Peh, Princeton, USA

Technical Scope

Papers are solicited which address new and previously unpublished results in the following areas.  Proposals for tutorial papers and panel sessions are also invited. The best paper will be acknowledged with a best paper award. A special section related to the theme of the conference in the IEEE Transactions on VLSI Systems.

  • Network architecture (topology, routing, arbitration,...)
  • Power and energy issues in NoC
  • NoC case studies, application-specific NoC design
  • Timing, synchronous / asynchronous communication
  • NoC reliability issues
  • O/S support for NoC
  • Metrics and benchmarks for NoCs
  • NoC Network interface issues
  • Modeling, simulation, and synthesis of NoCs
  • Network-on-chip design methodologies
  • NoC Quality of Service
  • NoC support for CMP / MPSoC
  • NoC support for memory access
  • NoCs for  FPGAs and structured ASICs
  • Programming models
  • Mapping of applications onto NoCs
  • Novel interconnect links / switches / routers
  • Signaling and circuit design for NoC links
  • Physical design of interconnect and NoC
  • NoC design tools

PAPER SUBMISSION

Electronic paper submission requires a full paper, up to 10 double-column IEEE format pages, including figures and references.

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Program

Hotel & Travel Information

Call for papers (pdf)

Committees

Registration

Submission

TVLSI Special Section on NoCs (pdf)

DATE 2006 NoC workshop

 

       

Sponsored by: IEEE Circuits and Systems Society, Council for EDA, ACM Special Interest Group on Computer Architecture (SIGARCH), ACM Special Interest Group on Embedded Systems (SIGBED), Silistix Inc.

 

Important Dates

  • Deadline for paper submission: Friday, December 1, 2006 (automatic extension to  December 10, 2006) 

  • Notification of acceptance:
    Monday, February 5, 2007

  • Deadline for final version:
    Sunday, March  4, 2007